The Cyrix 6x86(tm) processor family offers the highest level of performance available for desktop PCs today. Through the use of innovative, sixth-generation architectural techniques, the 6x86 processors achieve best-in-class performance that surpasses the Pentium(r) processor in each performance class.
The superscalar, superpipelined 6x86 processor, available in P200+, P166+, P150+, P133+ and P120+ performance classes, is optimized to run both 16-bit and 32-bit software. It is fully compatible with the x86 instruction set and delivers industry-leading performance running Windows(r) 95, Windows NT, Windows, OS/2(r), DOS, Solaris UNIX(r) and other operating systems. The Cyrix 6x86 processor is optimized for both 16-bit and 32-bit applications. Our goal is to offer users of 6x86-based PCs an easy path to higher performance for Windows NT and to MMX technology that protects today's PC investment. The next version of Cyrix's 6x86 processor, code-named M2, will provide optimum performance on 32-bit software and will be fully MMX compatible. This new processor will leverage today's 6x86 motherboard platforms, allowing plug-in upgrades for today's buyers of 6x86-based PCs. Purchasers can buy a 6x86-based PC now, with a guaranteed path to future technology via an M2 upgrade. (See The Future's Built In white paper). The Cyrix 6x86 processor achieves top performance through the use of two optimized superpipelined integer units and an on-chip FPU. The integer and floating point units are optimized for maximum instruction throughput by using advanced architectural techniques including register renaming, out-of-order completion, data dependency removal, branch prediction and speculative execution. These design innovations eliminate many data dependencies and resource conflicts to achieve high performance when executing existing non-recompiled software programs as well as future x86-compatible code. While the 6x86 achieve superior performance with existing software, it takes
advantage of any recompiled code to gain an additional 5-10% performance increase. Features and Benefits
Provides two pipelines to execute multiple instructions in parallel for faster processing and higher performance. 6x86 Processor Pentium Pro Processor Pentium Processor Full x86 Instruction Set Optimization X Superscalar X X X Superpipelined X X Register Renaming X X Data Dependency Removal X X Multi-Branch Prediction X X Speculative Execution X X Out-of-Order Completion X X 80-Bit Floating Point Unit X X X 16K Primary Cache X X X Superpipelining Increases the number of pipeline stages to avoid execution stalls and keep information flowing faster for higher frequency scalability. Register Renaming Provides temporary data storage for instant data availability without waiting for the CPU to access the on-chip cache or main system memory. Data
Dependency Removal Provides instruction results to both pipelines simultaneously so that neither pipeline is stalled. Multi-Branch Prediction Boost processor performance by predicting with high accuracy the next instructions needed. Speculative Execution Allows the pipelines to continuously execute instructions following a branch without stalling the pipelines. Out-of-Order Completion Lets the faster instruction exit the pipeline out of order, saving processing time without disrupting program flow. 80-bit
Floating Point Unit Provides high performance by speculatively executing FPU and integer instructions in parallel. 16-KB
Unified WB Cache Clocking 2x, 3x bus-to-core clock multiplier L1 Cache 16-KByte; write-back; 4-way associative; unified instruction and data; dual-port address Bus 64-bit external data bus; 32-bit address bus Pin/Socket P54C socket compatible (296-pin PGA) Compatibility Fully compatible with x86 operating systems and software including Windows 95, Windows, Windows NT, OS/2, DOS, Solaris and UNIX Floating Point Unit 80-bit with 64-bit interface; parallel execution; uses x87 instruction set; IEEE-754 compatible Voltage 3.3V core with 5V I/O tolerance Power Management System Management Mode (SMM); hardware suspend; FPU auto-idle Multiprocessing Supports SLiC/MP(TM) and OpenPIC(TM) interrupt architecture Burst Order 1-plus-4 or linear burst